Dual output capacitance interface circuit

ABSTRACT

A dual output capacitance interface circuit ( 100 ) based on switched capacitor circuits and charge subtraction technique provides both voltage output ( 104 ) and frequency output ( 106 ). The circuit is programmable independently with sensitivity and offset adjustment, and is insensitive to fixed stray capacitance. Temperature compensation methods are described.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of commonly-owned, copendingU.S. Provisional Patent Application No. 60/091,909, filed Jul. 7, 1998by Ko et al.

Attention is directed to commonly-owned, copending PCT PatentApplication No. 09/743,432, entitled METHOD OF FABRICATING SILICONCAPACITIVE SENSORS filed on even date herewith.

TECHNICAL FIELD OF THE INVENTION

The invention relates to circuits for interfacing with and derivingusable signals from transducers, more particularly capacitive forcetransducers such as pressure transducers, more particularly touch modecapacitive pressure sensors (“TMCPS”).

BACKGROUND OF THE INVENTION

Capacitive pressure sensors typically include a pair of conductiveelements, one of which is a fixed substrate another of which is aflexible diaphragm. In a conventional capacitive pressure sensor, aspressure increases a gap between the diaphragm and the underlyingsubstrate decreases, and the capacitance of the sensor increases. Thesensor is normally operated in a pressure range wherein the diaphragm iskept from actually contacting the underlying substrate. These sensorsnormally exhibit nonlinear characteristics. This inherent non-linearityhas led to the development of many linearization schemes using complexand costly interface circuits which include analog circuits andamplifiers, segment linearization, microprocessor and ROM matrixlinearization, etc.

Another type of capacitive pressure sensor is the touch mode capacitivepressure sensor (“TMCPS”). In touch mode operation, the diaphragm of thecapacitive pressure sensor touches the underlying substrate which iscovered by a thin insulating layer. As pressure increases, the contactarea increases. The major component of output capacitance is thecapacitance of the touched area with a thin layer of isolation layerwhich gives a larger capacitance per unit area compared to the air-gapcapacitance in the untouched area. The touch mode device was developedto withstand harsh industrial environment, and with one or two orders ofmagnitude higher sensitivity than the normal (non-touch) mode operationin the near linear operation range, so that some of the stray capacityeffects can be neglected. Advantages of touch mode capacitive pressuresensors include near linear output characteristics, large over-rangepressure capability and robust structure that make them capable towithstand harsh industrial field environments. One application ofinterest for pressure sensors generally, and touch mode capacitivepressure sensors in particular, is in conjunction with an RF transponderinside a pneumatic tire.

Examples of capacitive pressure sensors can be found in U.S. Pat. No.3,993,939 (November 1976), U.S. Pat. No. 5,528,452 (June 1996), U.S.Pat. No. 5.656,781 (August 1997), and U.S. Pat. No. 5,706,565 (January1998).

A number of different constructions for touch mode capacitive pressuresensors (TMCPS) have been successfully designed and fabricated,including a silicon-glass TMCPS using anodic bonding technique toassemble a silicon diaphragm and a glass substrate with a metallizedelectrode, a silicon-silicon TMCPS using silicon fusion bonding toassemble a silicon diaphragm and silicon substrate, and a polysiliconTMCPS using surface micromachining technology. The present invention isparticularly applicable to obtaining usable signals from a siliconfusion bonded capacitive pressure sensor (SFBCPS) such as is disclosedin Touch mode capacitive pressure sensors. Ko and Wang, published byElsevier, in Sensors and Actuators 2303 (1999), as well as in theaforementioned commonly-owned, copending PCT Patent Application Ser. No.09/743,432 entitled METHOD OF FABRICATING SILICON CAPACITIVE SENSORS,filed on even date herewith. As discussed in the Elsevier article:

“FIG. 8 shows the outline of major steps of the fabrication of SFBCPS.Two silicon wafers are needed to make silicon fusion bonded capacitivepressure sensors. On wafer A, cavities are formed by silicon etching todefine the gap. The bottom electrode on wafer A is formed by borondiffusion on the bottom of the cavity. A capacitive absolute pressuresensor needs an electrode feedthrough from a hermetically sealed cavity.In the design, the electrode feedthrough is lain down in a groove in thefeedthrough region. (The groove is sealed after the bonding and etchingprocesses). The isolation between two electrodes of the sensor isrealized by the thermal oxide on the bonding surface. Due to dopingconcentration dependent oxidation, there is usually a step generated inthe feedthrough region if the feedthrough electrode is on the surface.This will cause difficulties for silicon fusion bonding and hermeticsealing. The P+ doped electrode lain down in a groove, on the otherhand, will not disturb the silicon fusion bonding surface even with athick oxide growth. An extra sealing process by LTO deposition (400mTorr, 450(C) is used to get a hermetically sealed reference cavity ofthe sensor after diaphragm formation. The pressure inside the cavity isaround 150 mTorr after the sealing process. On wafer B, heavily borondoped diaphragm layer is formed by diffusion using solid source BN.After CMP, wafers A and B are bonded using Si fusion bonding, annealedat 1000 (C for 1 hour. P+ etch-stop technique is then used to fabricatethe diaphragm with the designed thickness.”

“The process discussed before can be simplified to a three-layerprocess. The structure of the fabricated sensor is illustrated in FIG.10. The substrate as whole will be used as the bottom electrode. The gapis defined by the thickness of thermally grown oxide. Since there is noelectrode feedthrough required, the hermetically sealed reference cavitycan be formed by silicon to silicon fusion bonding without introducingextra processes. There are two capacitors constructed on the sensorchip. One is constructed by silicon diaphragm and the substrateseparated by a reference cavity plus the surrounding bonding area. Thiscapacitor is pressure sensitive. The other is constructed by silicondiaphragm and the substrate separated by the oxide in the rest of thebonding area. It is insensitive to pressure and can be used as areference capacitor. The sensor chip is 1.0 mm×1.5 mm×0.4 mm in size.The diaphragm sizes range from 300 to 400 (mn in diameters. The processstarts with the P-type substrate silicon wafer with 2.2-(m thermallygrown oxide. The thickness of the oxide determines the initial gap ofthe capacitive pressure sensor. The oxide in cavity area is etched usingRIE, which can give very vertical sidewall after etching. The samethickness of oxide on the backside wafer can be used not only as wetsilicon etch mask, but also compensates the stress in the front sideoxide so that the wafer can keep flat for the silicon fusion bonding.After cavity formation, a 0.1-(m thick oxide is grown for the electricalisolation after the diaphragm touches the bottom. The top silicon waferwith a well-defined thickness of heavily doped boron is then bonded tothe cavity patterned substrate wafer using silicon fusion bondtechnique. No alignment is required during the bonding. Following thebonding, the Si—Si “wafer” is immersed in a dopant-dependent etchant(such as EDP, KOH and TMAH) to dissolve the silicon of the top waferexcept the P+ layer. The P+ layer is then patterned to form the twocapacitors and open the substrate contact window. Al contact pads areformed in the end using lift-off technique. This process utilizessingle-side processing of silicon wafers. It only requires threenon-critical masking steps and can produce very high yield.”

It has been observed that one drawback of the silicon fusion bondedcapacitive pressure sensors is that they have large zero-pressurecapacitance, which limits applications of some capacitive interfacecircuits. The large zero-pressure capacitance originates from the largebonding area and the isolation material with a large dielectric constantsurrounding the diaphragm. At zero-pressure, since the deflection of thediaphragm is small, the gap distance between diaphragm and the electrodeon the bottom electrode is large. Therefore the capacitance of theair-gap capacitor contributes a small part to the overall capacitance atzero-pressure. The zero-pressure capacitance is mainly determined by thebonding area required to ensure the hermetic seal and mechanicallysupport of the diaphragm. In the current design, the measuredzero-pressure capacitance of the fabricated sensor is 7.3 pF, of whichthe bonding area contributes about 80%.

U.S. Pat. No. 4,104,595 (August 1978), incorporated in its entirety byreference herein, discloses a signal translating circuit for variablearea capacitive pressure transducer. The circuit translates thecapacitance change of a variable area capacitive transducer into a d-cvoltage change. The transducer has two electrodes. As a force is appliedto a deformable one of two electrodes, there is a change in theeffective contact area between the electrodes in accordance with theapplied pressure, producing a resulting change in capacitance. Thesignal translating circuit produces a d-c output signal which varies asa function of the transducer capacitance change.

U.S. Pat. No. 4,392,382 (July 1983), incorporated in its entirety byreference herein, discloses a linearized electronic capacitive pressuretransducer. A variable capacitance pressure sensor (C_(X)) and areference capacitor (C_(R)), and associated circuitry, provide atemperature compensated output signal which has a substantial linearvariation as a function of sensed pressure.

U.S. Pat. No. 4,446,447 (May 1984), incorporated in its entirety byreference herein, discloses a circuit for converting pressure variationto frequency variation which includes a reference oscillator and asensor oscillator coupled to a digital mixer. The reference oscillatorincludes a reference capacitor and a reference resistor. The sensoroscillator has a variable sensor timing capacitor and a sensor resistor.

U.S. Pat. No. 4,820,971 (November 1989), incorporated in its entirety byreference herein, discloses a precision impedance measurement circuitproviding an output voltage (Vout) as a function of a capacitance (Cx)of a condition-sensing capacitor, and also describes the use of areference capacitor having a capacitance (Co) which is unaffected by thesensed condition is disclosed.

BRIEF DESCRIPTION (SUMMARY) OF THE INVENTION

It is an object of the present invention to provide method and apparatusfor interfacing with and deriving usable signals from transducers, moreparticularly capacitive force transducers such as pressure transducers,more particularly touch mode capacitive pressure sensors (“TMCPS”), asdefined in one or more of the appended claims and, as such, having thecapability of being implemented in a manner to accomplish one or more ofthe subsidiary objects.

According to the invention, a dual output capacitance interface circuit(100, FIG. 1) provides a voltage output (104) and a frequency output(106), each of which is related to a capacitance value of acondition-sensitive capacitance (Cx), such as a touch-mode capacitivepressure sensor. A capacitance-to-current (C-I) sub-circuit 110 convertscapacitance to current. A current-to-frequency (I-F) sub-circuit (112)converts current to frequency signal. A current-to-voltage (I-V)sub-circuit (114) converts current to a DC voltage.

According to an aspect of the invention, the capacitance-to-current(C-I) converter comprises three capacitor controlled current sourcescontrolled by a three-phase non-overlapping clock (116, FIG. 9). Thethree-phase non-overlapping clock (FIG. 9) may be driven by a clockgenerator (FIG. 10) comprising a Schmitt trigger.

According to an aspect of the invention, the current-to-frequency (I-F)converter (112, FIG. 5A) comprises a Schmitt trigger.

According to an aspect of the invention, the circuit is programmableindependently with sensitivity and offset adjustment, and is insensitiveto fixed stray capacitance.

The dual output capacitance interface circuit (100) is based on switchedcapacitor circuits and charge subtraction techniques for providing thevoltage (104) and frequency (106) outputs. The circuit is programmableindependently with sensitivity and offset adjustment, and is insensitiveto fixed stray capacitance. Temperature compensation methods aredescribed.

Other objects, features and advantages of the invention will becomeapparent from the description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will be made in detail to preferred embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings (FIGURES). The drawings are intended to be illustrative, notlimiting. Although the invention will be described in the context ofthese preferred embodiments, it should be understood that it is notintended to limit the spirit and scope of the invention to theseparticular embodiments.

Certain elements in selected ones of the drawings may be illustratednot-to-scale, for illustrative clarity.

Often, similar elements throughout the drawings may be referred to bysimilar reference numerals. For example, the element 199 in a FIGURE (orembodiment) may be similar in many respects to the element 299 inanother FIGURE (or embodiment).Such a relationship, if any, betweensimilar elements in different FIGURES or embodiments will becomeapparent throughout the specification, including, if applicable, in theclaims and abstract.

In some cases, similar elements may be referred to with similar numbersin a single FIGURE. For example, a plurality of elements 199 may bereferred to as 199 a 199 b, 199 c, etc.

The cross-sectional views, if any, presented herein may be in the formof “slices”, or “near-sighted” cross-sectional views, omitting certainbackground lines which would otherwise be visible in a truecross-sectional view, for illustrative clarity.

The structure, operation, and advantages of the present preferredembodiment of the invention will become further apparent uponconsideration of the following description taken in conjunction with theaccompanying drawings, wherein:

FIG. 1 is a block diagram of an embodiment of a Dual Output CapacitanceInterface Circuit (“interface circuit”), according to the invention;

FIGS. 2, 3 and 4 are simplified schematics illustrating the operationand an implementation of a capacitance-to-current converter sub-circuitof the interface circuit illustrated in FIG. 1, according to theinvention;

FIG. 5A is a simplified schematics illustrating the operation and animplementation of a current-to-frequency (I-F) converter sub-circuit ofthe interface circuit illustrated in FIG. 1, according to the invention;

FIG. 5B is a wave form diagram for the current-to-frequency converter,according to the invention;

FIG. 6 is a schematic for a configuration of a CMOS Schmitt triggercircuit, according to the invention;

FIG. 7 is a state diagram of a three-phase clock generator sub-circuitof the interface circuit illustrated in FIG. 1, according to theinvention;

FIG. 8 is a true value table for the three-phase clock generatorsub-circuit of the interface circuit illustrated in FIG. 1, according tothe invention;

FIG. 9 is a schematic of an implementation of the three-phase clockgenerator sub-circuit of the interface circuit illustrated in FIG. 1,according to the invention;

FIG. 10 is a schematic of a Schmitt oscillator (input clock generator)for providing a high duty cycle pulse for the three-phase clockgenerator sub-circuit of FIG. 9, according to the invention;

FIG. 11 is a timing diagram for the three-phase clock generatorsub-circuit of FIG. 9 and the Schmitt oscillator of FIG. 10, accordingto the invention,

FIG. 12 is a graph showing a Pspice-simulated resolution of a C-Fconverter, according to the invention;

FIG. 13 is a graph showing a Pspice-simulated temperature characteristicof a threshold voltage for a Schmitt trigger, according to theinvention;

FIGS. 14A and 14B are graphs showing simulated drain current temperaturecharacteristics for a pMOS, at Vgs=0 v and Vgx=1.8115 v, respectively,according to the invention;

FIG. 15 is a simplified schematic of a modified clock generator withtemperature compensation, according to the invention;

FIG. 16 is a graph showing a Pspice-simulated temperature characteristicof a clock generator with temperature compensation, according to theinvention;

FIG. 17 is a graph showing temperature characteristics of a C-Fconverter without temperature compensation, according to the invention;

FIG. 18A is a simplified schematic showing a currentdifference-to-voltage converter, according to the invention;

FIG. 18B is simplified schematic of a small signal equivalent circuitfor a current difference-to-voltage converter, according to theinvention;

FIG. 19 is a simplified schematic of a reference current generator for acurrent difference-to-voltage converter, according to the invention; and

FIG. 20 is a graph illustrating characteristics of the dual outputconverter of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a block diagram of an embodiment of the Dual OutputCapacitance Interface Circuit (“interface circuit”) 100 of the presentinvention. Generally, the circuit 100 has an input 102, to which isconnected a variable capacitance (Cx), and has two outputs—a voltageoutput 104 and a frequency output 106, both of which vary according tothe value of the capacitance (Cx) on the input 102 of the interfacecircuit 100. The interface circuit 100 comprises four major functionalblocks (sub-circuits):

a capacitance-to-current (C-I) converter 110 (capacitor-controlledcurrent source) which converts the measured capacitance (Cx) to acurrent signal;

a current-to-frequency (I-F) converter 112 which is used to convert thecurrent from the C-I converter 110 to a frequency signal on the output106;

a current-to-voltage (I-V) converter 114 (followed by a buffer 115)which is used to convert the current from the C-I converter 110 to a DCvoltage signal on the output 104; and

a three-phase clock generator 116, driven by an oscillator 118controlled by a capacitor (Cosc), which provides a three-phasenon-overlapping clock to control the charging/discharging process of thecapacitance-to-current (C-I) converter 110. No reset is necessary toinitiate the three-phase clock. The transition of the states is designedto avoid any simultaneous high state of the three phases.

Capacitance-to-Current (C-I) Converter

FIGS. 2, 3 and 4 are simplified schematics illustrating the operationand an implementation of the capacitance-to-current (C-I) converter 110of FIG. 1.

A modified switched-capacitor emulated resistor may be used to implementthe capacitor controlled current source, and is shown in FIG. 2.Switches S₁ and S₂ are controlled by a non-overlapping two-phase clock(not shown). During phase 1, switch S₁ is closed and switch S₂ isopened. The capacitor, C, is charged to V₁ at the end of phase 1. Thecharge on the capacitor C is CV₁ During phase 2, the switch S₁ is openedand the switch S₂ is closed. The charge on the capacitor C will becomeQ=CV₂ at the end of phase 2. The net charge transferred in one clockcycle is CV₁−CV₂. If the process continues, the average current flowingbetween V₁ and V₂ is (CV₁−CV₂)ƒ=(V₁−V₂)ƒC, where ƒ is the cycling clockfrequency. The equivalent resistance between V₁ and V₂ is 1/ƒC. Byreplacing V₂ with a MOSFET transistor. M₁, as shown in FIG. 3, theaverage current flow through the transistor M₁ is (V₁−V_(T))ƒC, whereV_(T) is the threshold voltage of the MOSFET providing the adequatesettling time is allowed. Since transistors M₁ and M₂ are connected as acurrent mirror, the current flowing through M₂ will be the same as thecurrent flowing through M₁ (ignoring a finite output resistance for M₂).

The capacitance-to-current (C-I) converter 110 can be constructed bythree capacitor controlled current sources as shown in FIG. 4. Thecircuit is controlled by a three-phase non-overlapping clock (116). Inphase 1, switches S₁ and S₂ are closed. Capacitors C_(x) and C_(o) arecharged to voltages V_(g) and V_(o), respectively. In phase 2, theswitches S₃ and S₄ are closed. The charge in the capacitor C_(o) isdischarged through the transistor M₁. The same amount of charge will bedrawn from the capacitor C_(x) through the transistor M₂ in the sametime period when the capacitor C_(o) is discharged, providing that thetransistor M₂ remains saturated. The charge left on the capacitor C_(x)at the end of phase 2 is Q=V_(g)C_(x)−(V_(o)−V_(T))C_(o), assuming thatthe charge, V_(g)C_(x), is larger than the charge, (V_(o)−V_(T))C_(o).The remaining voltage across the capacitor C_(x) isQ/C_(x)=V_(g)−(V_(o)−V_(T))(C_(o)/C_(x) ). During phase 3, the switch S₅is closed, and the average current flowing through the transistor M₃ is:$\begin{matrix}\begin{matrix}{I = \quad {\left\lbrack {V_{g} - {\left( {V_{o} - V_{T}} \right){C_{o}/C_{x}}} - V_{T}} \right\rbrack {fC}_{x}}} \\{= \quad {\left\lbrack {{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{o}}} \right\rbrack f}} \\{= \quad {{{f\left( {V_{g} - V_{T}} \right)}C_{x}} - {{f\left( {V_{o} - V_{T}} \right)}C_{o}}}} \\{= \quad {{K_{1}C_{x}} - {K_{2}C_{o}}}} \\{= \quad {{K1C}_{x} - K_{3}}}\end{matrix} & \text{(Eqn.~~1)}\end{matrix}$

where K₁=ƒ(V_(g)−V_(T)), K₂=ƒ(V_(o)−V_(T)), K₃=ƒ(V_(o)−V_(T))C_(o),assuming that threshold voltages of the transistors M₁, M₂ and M₃ arethe same.

Hence, the current I, flowing through the transistor. M₃ is related to(a measure of) the capacitance C_(x). The current I is also related toboth ƒV_(g) and ƒV_(o)C_(o), which makes it possible to adjust thecurrent by two external parameters, V_(g) and V_(o)C_(o), independently.The V_(o)C_(o) is used to adjust reference or offset current, whileV_(g) is used for gain control of C-I converter 110.

Current-to-Frequency (I-F) Converter

FIGS. 5A, 5B and 6 illustrate the operation and an implementation of thecurrent-to-frequency (I-F) converter 112 of FIG. 1.

FIG. 5A is a simplified schematic illustrating the operation and animplementation of the current-to-frequency (I-F) converter 112 of FIG.1. An output portion of the C-I converter 110, including the transistorsM₃ and M₄ is shown to the left of a dashed line. Thecurrent-to-frequency (I-F) components are shown to the right of thedashed line.

A Schmitt trigger is used to implement current-to-frequency (I-F)conversion. The Schmitt trigger has two trigger points, i.e., highthreshold voltage, V_(H), and low threshold voltage, V_(L). If the inputvoltage of a Schmitt trigger varies from low to high, the output voltagewill change from high to low when the input reaches the high thresholdvoltage. If the input voltage varies from high to low, the outputvoltage will change from low to high when the input reaches the lowthreshold voltage. The input voltage of the Schmitt trigger in the I-Fconverter is the voltage on a capacitor, C_(st), which is charged by acurrent source. Using average current I in equation Eqn. 1, which isrelated to the capacitance C_(x) measured, to charge and discharge thecapacitor C_(st), a symmetric square wave can be obtained from theoutput of the Schmitt trigger, as shown in the graphs of FIG. 5B. Thecharge current source and the discharge sink can be realized by twocurrent mirrors controlled by two switches, as shown in FIG. 5A. Thetransistors M_(f1), M_(f2) and the switch S₁₁ are used to generate thecharging current. When the voltage on the capacitor C_(st) is less thanthe high threshold voltage, V_(H), the output of the Schmitt trigger ishigh, thus the output F_(out) is low. Using the high output signal ofthe Schmitt trigger to turn the switch S₁₁ on, the current through thetransistor M_(f2), which is equal to the current I, will charge thecapacitor C_(st) until the voltage on the capacitor C_(st) reaches theV_(H). At this time, the Schmitt trigger toggles. The output of theSchmitt trigger becomes low and the output F_(out) becomes high. Usingthe output signal F_(out) to turn on the switch S₁₂, the capacitorC_(st) is discharged through the transistor M_([4]f3). The dischargingcurrent is also the mirrored current, I. The charging and dischargingtime are the same, which is equal to V_(c)C_(st)/I. Thus, the outputfrequency, F_(out), can be expressed as: $\begin{matrix}{F_{out} = {\frac{I}{2V_{c}C_{st}} = {\frac{{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{o}}}{2V_{c}C_{st}}f}}} & \text{(Eqn.~~2)}\end{matrix}$

where V_(c) is the threshold voltage of the Schmitt trigger, which isthe difference between V_(H) and V_(L).

The CMOS Schmitt trigger is suitably constructed by six CMOS transistorsMS1, MS2, MS3, MS4, MS5 and MS6, as shown in FIG. 6. Assuming that theinput voltage V_(in) is zero. then transistors MS1 and MS2 are off,transistors MS4 and MS5 are in the linear mode of operation, but thevoltage drops at each transistor are zero because there is no currentfollowing. The output voltage is V_(DD). Transistor MS3 is on at thistime. Therefore it also does not carry current since V_(n)=V_(DD). WhenV_(in) rises above the threshold voltage of nMOS, transistor MS1 turnson and starts to conduct. The potential V_(n), which is the source-drainvoltage of transistor MS1, is starting to decrease with the gate voltageV_(in) increasing. The trigger operation starts when V_(in) reaches thevalue V_(Hi). At this point, due to the simultaneous increase of V_(in)and decrease of V_(n), the transistor MS2 turns on. The trigger startsto operate as a linear circuit with positive feedback. Thus thetransition from high to low is very fast. The same situation happenswhen the V_(in) varies from high to low. The V_(Hi) and V_(Li) can beobtained from the equations shown as follows: $\begin{matrix}{\frac{k1}{k3} = {\left( \frac{V_{DD} - V_{Hi}}{V_{Hi} - V_{m)}} \right)^{2}\quad \text{thus}}} & \text{(Eqn.~~3)} \\{V_{Hi} = \frac{V_{DD} + {\sqrt{\frac{k1}{k3}}V_{Tn}}}{1 + \sqrt{\frac{k1}{k3}}}} & \text{(Eqn.~~4)} \\{{\frac{k4}{k6} = {\left( \frac{V_{Li}}{V_{DD} - V_{Li} - {V_{TP}}} \right)^{2}\quad \text{thus}}},} & \text{(Eqn.~~5)} \\{V_{Li} = {\frac{V_{DD} - {V_{Tp}}}{1 + \sqrt{\frac{k4}{k6}}}\sqrt{\frac{k4}{k6}}}} & \text{(Eqn.~~6)}\end{matrix}$

where ki (i=1-4) are the width length ratio of MOSFETs; V_(DD) is powersupply; V_(Tn) and V_(Tp) are the threshold voltage of nMOS and pMOS,respectively.

The two equations Eqn. 4 and Eqn. 6 can be used to determine the highthreshold voltage and low threshold voltage of the Schrnitt trigger. Onthe other hand, these two equations can also be used to designtransistors' sizes to get threshold voltages required.

The voltages V_(Hi) and V_(Li) are, in fact, the beginning of triggeringoperation. The real triggering occurs at approximate but differentvoltage V_(H) and V_(L). The difference depends on choice of theparameters k2 and k5 and can be estimated as follows: $\begin{matrix}{{\Delta \quad V_{H}} = {{V_{H} - V_{Hi}} = \frac{V_{DD} - V_{Hi} - {V_{Tp}}}{\frac{k_{2}}{k_{5}} + \frac{k_{2}}{k_{4}}}}} & \text{(Eqn.~~7)} \\{{\Delta \quad V_{L}} = {{V_{L} - V_{Li}} = {- \frac{V_{Li} - V_{Tn}}{\frac{k_{5}}{k_{2}} + \frac{k_{5}}{k_{1}}}}}} & \text{(Eqn.~~8)}\end{matrix}$

where ki (i=1, 2, . . . , 5) are the width:length ratios of the MOSFETtransistors MS1-MS6. In this example: the transistor MS1 has awidth:length ratio of 18:2 (6/2 ), the transistor MS2 has a width:lengthratio of 18:2 (18/2), the transistor MS3 has a width:length ratio of18:2 (21/2), the transistor MS4 has a width:length ratio of 18:2 (18/2),the transistor MS5 has a width:length ratio of 18:2 (90/2), and thetransistor MS6 has a width:length ratio of 18:2 (36/2).

It can be seen from the equations above that to reduce ΔV_(H) andΔV_(L), the k2/k5 should be kept constant and both k2/k4 and k5/k1should be increased.

Assume that a Schmitt trigger has threshold values of V_(Hi)=3.5 v andV_(Li)=1.7 v. The circuit operates at V_(DD)=5 v. Using MOSIS processparameters μ_(n)C_(ox)/2=26.5, μ_(p)C_(ox)/2=9.6, V_(Tn)=0.7412,V_(Tp)=−0.9002 [4.7] and equations Eqn. 4-Eqn. 8, the Schmitt trigger isdesigned. The sizes of transistors (W/L) are marked in FIG. 6. Thecalculated (from equation 4.4-4.8), Pspice simulated and measuredthreshold voltages are listed in the following table (TABLE 1).

TABLE 1 Parameters of Schmitt trigger Calculation Simulation MeasurementV_(Hi) (v) 3.516 N/A N/A V_(H) = V_(Hi) + Δ V_(H) (v) 3.692 3.736 3.682V_(Li) (v) 1.698 N/A N/A V_(H) = V_(Li) + Δ V_(L) (v) 1.566 1.528 1.586Fall time (ns) N/A 21.58 N/A Rise time (ns) N/A 28.59 N/A

Three-Phase Clock

FIG. 7 is a state diagram, FIG. 8 is a true value table and FIG. 9 is aschematic of an implementation of the three-phase clock generator 116 ofFIG. 1. FIG. 10 is a schematic of a Schmitt oscillator (input clockgenerator) for providing a high duty cycle pulse for the three-phaseclock generator of FIG. 9. FIG. 11 is a timing diagram for thethree-phase, non-overlapping clock generator of FIG. 9 and the Schmittoscillator of FIG. 10.

A three-phase non-overlapping clock is employed in thecapacitance-to-frequency converter (the combination of the C-I converter110 and the I-F converter 112 comprise a capacitance-to-frequency (C-F)converter “110/112”) to control charging and discharging capacitors indifferent periods of time, as discussed hereinabove. The required statediagram of the clock is shown in FIG. 7. Each state represents onecombination of the three phases of the clock. Each logic numberrepresents the voltage level of a phase in the clock. A true value tablecan be obtained from the state diagram, as shown in FIG. 8. wherein Q1,Q2 and Q3 are the three phases of the clock. The clock preferably has“anti-lock” property, meaning that whatever state each phase of theclock has initially, the clock should be working properly in the righttransition sequence. The symbol “x” in the true value table of FIG. 8represents a “don't care” phase. Since the faulty states are thosestates which have more than one “1” output in the clock. If the clock isin one of those faulty states, the next state needs to be one of thestates which have only one “1”, or initial state (0 0 0). Therefore, thefaulty state (0 11) should go to any one of the states (0 0 0), (0 1 0),(1 0 0) and (0 0 1), for example. But only one “don't care” phase isallowed for one faulty state in the true value table in order to avoidgoing to another faulty state. By adding “don't care” phases on properplaces, logic equations of the clock can be simplified. If the clock isnot allowed to go to state (1 0 0) from the faulty state (0 1 1), thephase 1 must be follow the equation

Q _(1n) ={overscore (Q_(1(n−1)))} Q _(2(n−1)) {overscore(Q_(3(n−1)))}  (Eqn. 9)

However, if the clock can go to state (1 0 0) also, the logic equationcan be simplified as: $\begin{matrix}\begin{matrix}{Q_{\ln} = \quad {{\overset{\_}{Q_{1{({n - 1})}}}Q_{2{({n - 1})}}\overset{\_}{Q_{3{({n - 1})}}}} + {\overset{\_}{Q_{1{({n - 1})}}}Q_{2{({n - 1})}}Q_{3{({n - 1})}}}}} \\{= \quad {\overset{\_}{Q_{1{({n - 1})}}}Q_{2{({n - 1})}}}}\end{matrix} & \text{(Eqn.~~9.1)}\end{matrix}$

Using the same method, the logic equations for phases 2 and 3 can beobtained as

Q _(2n) ={overscore (Q_(1(n−1)))} {overscore (Q_(2(n−1)))}  (Eqn. 9.2)

 Q _(3n) =Q _(1(n−1)) {overscore (Q_(2(n−1)))}  (Eqn. 9.3)

The “don't care” phases are added in the true value table as shown inFIG. 8.

Two three-phase non-overlapping clock 116 can be constructed accordingto equations set forth above. An embodiment of a physical implementation(realization) for the clock is shown in FIG. 9. A high duty cycle clockis used as an input clock of the three-phase clock. Two edge-trigged Dflip-flops are used to control the transition timing. Since thetransition of D flip-flops occurs at the rising edge of the input clock,there will be no undesirable spike to cause erroneous turn-on ofswitches. The low period of input clock pulls all the outputs low, whichproduces the non-overlapping period between adjacent phases. Since theclock generator has “anti-lock” property, no reset is necessary toinitiate the clock.

FIG. 10 illustrates a Schmitt oscillator (clock generator) for providinga high duty cycle pulse for the three-phase clock generator of FIG. 9.The low period will be used to produce the non-overlapping period. Thehigh period is converted to the high period of each phase of thethree-phase clock by the sequence desired. The charging and dischargingof the capacitor C_(osc) is achieved by a non-symmetric inverter whosepMOS has a lower driving capacity than that of nMOS, so that C_(osc) canbe charged slowly up to the high threshold voltage of the Schmitttrigger to provide a long positive period of the pulse. FIG. 11illustrates the schematic timing diagram of the Schmitt trigger inputclock generator of FIG. 10 and the three-phase non-overlapping clockgenerator of FIG. 9. The ratio of (W/L)_(p)/(W/L)_(n) is 3/10. whichwill give the nMOS about 10 times driving power than the pMOSconsidering μ_(n)≈3μ_(p). Therefore, the duty cycle of the clock is90.9%.

Conversion of Capacitance-to-current

The conversion of capacitance-to-current is realized by the chargedifference on the measuring capacitor and the reference capacitor. Thecharging and discharging process are important in the conversion,especially the discharging process since it controls the total chargewhich can be converted to current. To simplify the discharging processanalysis, the resistance of the analog switch is represented by a linearresistor, R. When the voltage V_(DS) of a MOSFET is greater than thesaturation voltage which is V_(GS)−V_(T), the MOSFET works in thesaturation region. The first-order expression of the drain current canbe expressed as:

I=k′(V _(G) −V _(T))²  (Eqn. 10)${\text{where}\quad k^{\prime}} = {\frac{\mu \quad C_{ox}}{2}\frac{W}{L}}$

The gate voltage V_(G) can be expressed using saturation current by$\begin{matrix}{V_{G} = {\sqrt{\frac{1}{k^{\prime}}} + V_{T}}} & \text{(Eqn.~~11)}\end{matrix}$

By Kirchoff's law, we have $\begin{matrix}{V_{C} = {{{IR} + V_{G}} = {{IR} + \sqrt{\frac{I}{k^{\prime}}} + V_{T}}}} & \text{(Eqn.~~12.1)}\end{matrix}$

taking time derivative of both sides and substitute {square root over(I)} with Y, $\begin{matrix}{\frac{V_{C}}{t} = {{2{RY}\frac{Y}{t}} + {\frac{1}{\sqrt{k^{\prime}}}\frac{Y}{t}}}} & \text{(Eqn.~~12.2)}\end{matrix}$

substitute $\frac{V_{C}}{t}$

using the equation ${I = {{- C}\frac{V_{C}}{t}}},$

$\begin{matrix}{{- \frac{Y^{2}}{C}} = {{2{RY}\frac{Y}{t}} + {\frac{1}{\sqrt{k^{\prime}}}\frac{Y}{t}}}} & \text{(Eqn.~~12.3)} \\{{dt} = {{{- 2}{RC}\frac{dY}{Y}} - {\frac{C}{\sqrt{k^{\prime}}}\frac{dY}{Y^{2}}}}} & \text{(Eqn.~~13)}\end{matrix}$

integrating both sides from 0 to t. $\begin{matrix}\begin{matrix}{t = \quad {{\frac{C}{\sqrt{k^{\prime}}}\left( {\frac{1}{Y} - \frac{1}{Y_{0}}} \right)} + {2{RC}\quad \ln \quad \frac{Y_{0}}{Y}}}} \\{= \quad {{\frac{C}{\sqrt{k^{\prime}}}\left( {\frac{1}{\sqrt{I}} - \frac{1}{\sqrt{I_{0}}}} \right)} + {2{RC}\quad \ln \quad \frac{\sqrt{I_{0}}}{\sqrt{I}}}}} \\{= \quad {{\frac{C}{k^{\prime}}\left( {\frac{1}{V - V_{T}} - \frac{1}{V_{i} - V_{T}}} \right)} + {2{RC}\quad \ln \quad \frac{V_{i} - V_{T}}{V - V_{T}}}}}\end{matrix} & \text{(Eqn.14)}\end{matrix}$

The time, t, is the time required for the gate voltage started at V_(i)to drop to V. It can be observed that R has to be made small and k′ belarge in order to reduce the discharging time, t.

It is impractical to use low frequency in the capacitance-to-currentconverter to discharge the voltage on the capacitor to V_(T.) Based onthe fact that the rate at which the voltage on the capacitor drops isslow when the gate voltage is close to the threshold voltage [4.10], theproper operation frequency can be chosen to obtain a satisfied accuracy.Ideally, the total charge which is used in the conversion is(V_(g)−V_(T))C_(x), assuming the voltage on the capacitor C_(x) has beendischarged from V_(g) to V_(T) during the discharging process. If thedischarging time is not long enough, there is a residual voltage ΔV,which differs from V_(T) existed on C_(x). The charge is used in theconversion now is [V_(g)−(V_(T)+ΔV]C_(x)=[V_(g)−ΔV−V_(T)]C_(x), where ΔVis the residual voltage. The residual voltage during the dischargingprocess can be considered as a decreased charging voltage V_(g). Theoutput frequency error, because of the decreased V_(g) can be derived asfollowing:

Take derivative of Eqn. 2 respect to V_(g) $\begin{matrix}{\frac{\partial F}{\partial V_{g}} = {\frac{\frac{\partial I}{\partial V_{g}}}{2V_{c}C_{st}} = \frac{{fC}_{x}}{2V_{c}C_{st}}}} & \text{(Eqn.~~16.1)} \\{{\partial F} = {{- \frac{{fC}_{x}}{2V_{c}C_{st}}}{\partial V_{g}}}} & \text{(Eqn.~~16.2)} \\{\frac{\partial F}{F} = \frac{C_{x}{\partial V_{g}}}{{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{0}}}} & \text{(Eqn.~~16.3)}\end{matrix}$

The allowed variation of the charging voltage V_(g) is dependent on theaccuracy of the output required frequency. From equation Eqn. 16.3, wehave: $\begin{matrix}{{\partial V_{g}} = {\frac{\partial F}{F}\quad \frac{{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{o}}}{C_{x}}}} & \text{(Eqn.~~17)}\end{matrix}$

According to equation Eqn. 17, the maximum residual voltage ΔV on thecapacitor before the voltage is discharged to V_(T) can be determined.For an example, if the maximum error of output frequency is allowed tobe 0.1% in the measurement range of 10 pF. V_(g)=V_(o)=4.5 v, C_(ƒ)=1.0pF. The residual voltage can be allowed to be 3.24 mv. Using equationEqn. 14, the discharging time can be obtained when the V−V_(T) issubstituted by the residual voltage. Therefore, the operation frequencycan be determined by the calculated discharging time. The clockfrequency can be expressed in term of discharging time: $\begin{matrix}{f = \frac{1}{{3T_{dis}} + {2T_{\text{non}\text{-}\text{overlap}}}}} & \text{(Eqn.~~18)}\end{matrix}$

Other techniques to reduce ΔV can be developed so that the clockfrequency can be increased.

Resolution of the C-F Converter

The resolution of the C-F converter 110/112 is defined as the minimumcapacitance that the converter can detect. If the same voltage are usedfor V_(g) and V_(o), output frequency F in equation Eqn. 2 can besimplified as: $\begin{matrix}{F = \frac{\left( {V_{g} - V_{T}} \right)\left( {C_{x} - C_{o}} \right)f}{2V_{c}C_{st}}} & \text{(Eqn.~~19.1)}\end{matrix}$

When the measured capacitance C_(x) is increased by ΔC, the outputfrequency F ΔC can be obtained as: $\begin{matrix}{F_{\Delta \quad C} = \frac{\left( {V_{g} - V_{T}} \right)\left( {C_{x} + {\Delta \quad C} - C_{o}} \right)f}{2\quad V_{c}C_{st}}} & \text{(Eqn.~~19.2)}\end{matrix}$

The difference of output frequency is: $\begin{matrix}{{\Delta \quad F} = {{F_{\Delta \quad c} - F} = \frac{\left( {V_{g} - V_{T}} \right)f\quad \Delta \quad C}{2V_{C}C_{st}}}} & \text{(Eqn.~~19.3)}\end{matrix}$

The resolution of the converter can be expressed as: $\begin{matrix}{{\Delta \quad C} = {\frac{\Delta \quad F}{f}\quad \frac{2V_{C}C_{st}}{V_{g} - V_{T}}}} & \text{(Eqn.~~20)}\end{matrix}$

In the equation Eqn. 19, V_(c) is the threshold voltage of the Schmitttrigger and cannot be adjusted due to circuit configuration. However,the resolution of the converter, ΔC, can be designed by choosing theratio of C_(st)/ƒV_(g) under the condition that ΔF is greater than 1 Hzwhich is determined by the external measurement instrument. FIG. 12shows that the resolution of the C-F converter (110/112) can be 0.01 pFwhen the parameters of the circuit listed are chosen.

Temperature Characteristics Analysis

Temperature characteristics of the C-F converter 110/112 are discussedin this section in order to understand the temperature drift of thecircuit. The temperature sensitivity of all three sub-circuits,capacitance-to-current converter 110, current-to-frequency converter 112and clock generator 116, contribute to the temperature error of the C-Fconverter 110/112.

(a) Temperature Dependency of MOSFET Threshold Voltage, V_(T)

The threshold voltage of MOS transistors is sensitive to temperature. Itwill introduce temperature drift of the CMOS based circuits. Theparameter Φ_(F) plays a dominant role in the temperature dependency ofthe threshold voltage of MOS transistors. The temperature dependencyΦ_(F) is given by: $\begin{matrix}{\frac{\Phi_{F}}{T} = {\frac{1}{T}\left\lbrack {\Phi_{F} \pm {\left( {\frac{3}{2}\frac{kT}{q}} \right)\frac{E_{g0}}{2q}}} \right\rbrack}} & \text{(Eqn.~~20)}\end{matrix}$

in which “−” is used for an nMOS and “+” for a pMOS.

The parameter Φ_(F) always decreases in absolute value when thetemperature increases. The term E_(go) is dominant. As a result, for annMOS, Φ_(F) is positive and its dΦ_(F)/dT is negative. Since the nMOS isusually in the enhancement mode, its threshold voltage decreases inabsolute value. On the other hand, for a pMOS, Φ_(F) is negative anddΦ_(F)/dT is positive. The threshold voltage thus decreases in absolutevalue as well.

The temperature dependency of V_(T) can be given by $\begin{matrix}{\frac{V_{T}}{T} = {2 \pm {\frac{\gamma}{2\sqrt{\Phi_{F}}}\frac{\Phi_{F}}{T}}}} & \text{(Eqn.~~21)}\end{matrix}$

with “+” for a nMOS and “−” for a pMOS.

For a nMOS, the $\frac{\partial V_{T}}{\partial T}$

is negative and for a pMOS the $\frac{\partial V_{T}}{\partial T}$

is positive. But the absolute value of$\frac{\partial V_{T}}{\partial T}$

can be estimated as 2 mv/K.

(b) Temperature Dependency of Capacitance-to-current Converter

The temperature error of the C/I converter 110 comes from the thresholdvoltage of MOSFETs in current mirrors which are temperature dependent.From the equation Eqn. 1, the temperature error of the current convertedcan be expressed as: $\begin{matrix}{\frac{\partial I}{\partial T} = {{{\left( {{{- C_{x}}\frac{\partial V_{T}}{\partial T}} + {C_{o}\frac{\partial V_{T}}{\partial T}}} \right)f} + {\left\lbrack {{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{o}}} \right\rbrack \frac{\partial f}{\partial T}}} = {{{- \frac{\partial V_{T}}{\partial T}}\left( {C_{x} - C_{o}} \right)f} + {\left\lbrack {{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{o}}} \right\rbrack \frac{\partial f}{\partial T}}}}} & \text{(Eqn.~~22)}\end{matrix}$

The temperature error of the current is proportional to the temperaturedrift of the threshold voltage and clock frequency.

(c) Temperature Dependency of Schmitt Trigger Circuit

The current-to-frequency converter and the clock generator are realizedby the Schmitt trigger circuits. The temperature characteristics of thetwo sub-circuits are determined by the temperature dependency of theSchmitt trigger.

Using equations Eqn. 4 and Eqn. 6 the threshold voltage can be definedas $\begin{matrix}{V_{c} = {{V_{H} - V_{L}} = {\frac{V_{DD} + {\sqrt{\frac{k1}{k3}}V_{Tn}}}{1 + \sqrt{\frac{k1}{k3}}} - {\frac{V_{DD} - {V_{Tp}}}{1 + \sqrt{\frac{k4}{k6}}}\sqrt{\frac{k4}{k6}}}}}} & \text{(Eqn.~~23)}\end{matrix}$

The temperature error of Schmitt trigger is: $\begin{matrix}{\frac{\partial V_{c}}{\partial T} = {{\frac{\sqrt{\frac{k1}{k3}}}{1 + \sqrt{\frac{k1}{k3}}}\frac{\partial V_{Tn}}{\partial T}} + {\frac{\sqrt{\frac{k4}{k6}}}{1 + \sqrt{\frac{k4}{k6}}}\frac{\partial{V_{Tp}}}{\partial T}}}} & \text{(Eqn.~~24)}\end{matrix}$

The temperature error of the Schmnitt trigger is proportional to theerror of the threshold voltages of both pMOS and nMOS. The temperaturedrift can be determined as −1.525 mv/K according to equation Eqn. 24,where k1/k3=6/21 and k4/k6=18/36. FIG. 13 shows a Pspice simulationresult of the temperature characteristics of the threshold voltage ofthe Schmitt trigger circuit used in the converter.

(d) Temperature Error of the capacitance-to-frequency Converter

The temperature error of the capacitance-to-frequency converter 110/112comes from three major sub-circuits, the capacitance-to-currentconverter 110, Schmitt trigger (FIG. 10) and clock generator 116. Theoutput frequency is given by: $\begin{matrix}{F = \quad \frac{I}{2V_{c}C_{st}}} & \text{(Eqn.~~25)} \\\begin{matrix}{\frac{\partial F}{\partial T} = \quad {{\frac{1}{2V_{c}C_{st}}\frac{\partial I}{\partial T}} - {\frac{I}{2V_{c}^{2}C_{st}}\frac{\partial V_{c}}{\partial T}}}} \\{= \quad {\frac{1}{2V_{c}C_{st}}\left\{ {{{- \frac{\partial V_{Tn}}{\partial T}}\left( {C_{x} - C_{o}} \right)f} +} \right.}} \\{\quad \left. {{\left\lbrack {{\left( {V_{g} - V_{Tn}} \right)C_{x}} - {\left( {V_{o} - V_{Tn}} \right)C_{o}}} \right\rbrack \frac{\partial f}{\partial T}} - {\frac{1}{V_{c}}\frac{\partial V_{c}}{\partial T}}} \right\}} \\{= \quad {- {\frac{f}{2V_{c}C_{st}}\left\lbrack {{\left( {C_{x} - C_{o}} \right)\frac{\partial V_{Tn}}{\partial T}} +} \right.}}} \\{{\quad \left. {\frac{{\left( {V_{g} - V_{Tn}} \right)C_{x}} - {\left( {V_{o} - V_{Tn}} \right)C_{o}}}{V_{c}}\frac{\partial V_{c}}{\partial T}} \right\rbrack} +} \\{\quad {\frac{{\left( {V_{g} - V_{Tn}} \right)C_{x}} - {\left( {V_{o} - V_{Tn}} \right)C_{o}}}{2V_{c}C_{st}}\frac{\partial f}{\partial T}}}\end{matrix} & \text{(Eqn.~~26)}\end{matrix}$

As discussed before, both the threshold voltage of a nMOS and thethreshold voltage of a Schmitt trigger have negative temperaturecoefficients. It can be noticed from equation Eqn. 26 that the ∂V_(T)/∂Tand ∂V_(c)/∂T have opposite signs with ∂ƒ/∂T. Therefore, the temperatureerror of the C/F converter circuit can be compensated if the clockfrequency has an appropriate negative temperature coefficient. Atemperature compensation method based on the temperature controlledsaturation current of pMOS transistors is discussed in the followingsection.

Temperature Error Compensation for C-F Converter

For a MOSFET in saturation, the first-order expression of the draincurrent can be expressed as: $\begin{matrix}{I_{sat} = {\frac{\mu \quad C_{ox}}{2}\frac{W}{L}\left( {V_{GS} - V_{T}} \right)^{2}}} & \text{(Eqn.~~27)}\end{matrix}$

The temperature coefficient of the saturation current is determined bythe temperature coefficient of both mobility of carriers in theinversion layer and the threshold voltage, V_(T), of the MOSFET. Themobility of holes and electrons can be a strong function of temperature,depending on the doping level, given by μ=C_(μ)T^(−n) ^(_(μ)) whereC_(μ) and n_(μ) are constants. The temperature dependency of themobility itself is then given by; $\begin{matrix}{{\frac{1}{\mu}\frac{\mu}{T}} = {- \frac{n_{u}}{T}}} & \text{(Eqn.~~28)}\end{matrix}$

For low doping levels, the value of n_(μ) is about 1.5. The channel of aMOSFET has an average doping level that is at least the doping level ofbulk (i.e. strong inversion condition). Therefore, the bulk doping levelcan be used to estimate the value of n_(μ). The result usually is closeto 1.5.

Take time derivative to equation Eqn.27, $\begin{matrix}{\frac{\partial I_{sat}}{\partial T} = {{\frac{C_{ox}}{2}\frac{W}{L}\left( {V_{GS} - V_{T}} \right)^{2}\frac{\partial\mu}{\partial T}} - {\frac{\mu \quad C_{ox}}{2}\frac{W}{L}2\left( {V_{GS} - V_{T}} \right)\frac{\partial V_{T}}{\partial T}}}} & \text{(Eqn.~~29.1)}\end{matrix}$

Dividing I_(sat) on both sides, $\begin{matrix}{{\frac{1}{I_{sat}}\frac{\partial I_{sat}}{\partial T}} = {{\frac{1}{\mu}\frac{\partial\mu}{\partial T}} - {\frac{2}{V_{Gs} - V_{T}}\frac{\partial V_{T}}{\partial T}}}} & \text{(Eqn.~~29.2)}\end{matrix}$

Substituting equation Eqn. 28 into equation Eqn. 29.2, $\begin{matrix}{{\frac{1}{I_{sat}}\frac{\partial I_{sat}}{\partial T}} = {{- \frac{n_{\mu}}{T}} - {\frac{2}{V_{GS} - V_{T}}\frac{\partial V_{T}}{\partial T}}}} & \text{(Eqn.~~30)}\end{matrix}$

The two terms have different signs and can be compensating each other.It can be shown, theoretically and experimentally, that unique (anddistinct) gate voltage exists for a given MOSFET that the drain currenthas a zero temperature coefficient.

Letting ${{\frac{1}{I_{sat}}\frac{\partial I_{sat}}{\partial T}} = 0},$

the zero-temperature-coefficient gate-source voltage (V_(GSZ)) can bedetermined by: $\begin{matrix}{V_{GSZ} = {V_{T} - {\frac{2T}{n_{\mu}}\left( \frac{\partial V_{T}}{\partial T} \right)}}} & \text{(Eqn.~~31)}\end{matrix}$

For a pMOS made by MOSIS, the V_(T) is −0.9 v, using n_(μ)=1.5, the zerotemperature coefficient V_(GS) can be estimated as −1.7 v at 300 K.FIGS. 14A and 14B show the drain current of a pMOS simulated by Pspice.Using V_(GS)=−5 v in (a), the drain current changes from 161.055 μA to106.663 μA in the temperature range between 0 to 100° C. The maximumerror is 33.77%. Using V_(GS)=−1.8115 v in (b), the transistor keeps thedrain current of 11.779 μA at 0° C. and 100° C. The minimum draincurrent is 11.657 μA at 45° C. The maximum error is 1.035% with respectto the drain current at 0 ° C.

Using the principle discussed above, the clock generator used in theconverter can be modified to have a controllable temperaturecharacteristic. The diagram of the modified clock generator is shown inFIG. 15. As discussed hereinabove, the clock is realized by a Schmitttrigger. The input voltage of the Schmitt trigger is the voltage on thecapacitor. C_(st), charged and discharged by two MOSFETs. By biasing M₁at V_(GSZ), the charging current can be temperature stable. Since thecharging time is the dominant factor determining the clock period in thehigh duty cycle clock, only the transistor M₁ is biased to have a zerotemperature coefficient drain current to simplified the design.Transistor S_(c) is used as a switch (hence, the “S” nomenclature) tocontrol the charging process. When the output of the Schmitt trigger islow, the transistor S_(c) is “on” to connect power supply with aresistor network which gives the M₁ a biasing gate voltage at V_(GSZ).The capacitor C_(st) is charged via the transistor M₁ to the highthreshold voltage. When the output of the Schmitt trigger is high,transistors S_(c) and M₁ are off. Then the C_(st) is discharged via M₂at the maximum saturation current to the lower threshold voltage.Actually, M₁ needs to be biased at V_(GSZ)′, where |V_(GSZ)′| is greaterthan |V_(GSZ) |, so that it has a negative temperature coefficient inorder to compensate the temperature errors of the threshold voltage ofthe Schmitt trigger and capacitance-to-current converter (see Eqn. 26).FIG. 16 shows the Pspice simulation results of a clock frequency in thetemperature range of −25° C. to 100 ° C., where the M1 is biased at1.818 v. The relative error with respect to the frequency at 25° C. isless than ±0.5%. FIG. 17 shows the output frequency of thecapacitance-to-frequency converter when M1 is biased at differentvoltages. It can be shown that the temperature coefficient of theconverter can vary from positive to negative depending on how the biasvoltage of M1 is designed. TABLE 2 shows the relative temperature errorof the converter in the range of −25° C.-100° C., which is defined asfollowing: $\begin{matrix}{ɛ = {\frac{{F(T)} - {F\left( {25{^\circ}\quad {C.}} \right)}}{F\left( {25{^\circ}\quad {C.}} \right)} \times 100\%}} & \text{(Eqn.~~32)}\end{matrix}$

The simulated results were used to design the circuit of thecapacitance-to-frequency/voltage converter.

TABLE 2 Relative Temperature Error of C-F Converter V_(R) (v) nocompensation 3.203 3.005 2.809 Error % +/−14.16 +/−7.19 +/−0.67 +/−5.33

Capacitance-to-Voltage Converter

The current obtained from the capacitance-to-current (C-I) converter 110can also be used to provide DC voltage signal output 104. A combinationof the capacitance-to-current (C-I) converter 110 and current-to-voltage(I-V) converter 114 constitute a capacitance-to-voltage converter“110/114”.

A difference current-to-voltage (I-V) converter 114 is shown in FIG.18A. By using this circuit, a voltage output 104 can be obtained inaddition to the frequency output 106 from the capacitance-to-frequency(C-F) converter 110/112. The equivalent small signal circuit of the V-Icircuit is shown in FIG. 18B, where g_(mi), and r_(ki) are thetransconductance and loading resistance of the drain of the ith MOSFET,respectively. From the small signal circuit, we have,

V 1=(I 1−g _(m1) V 1)r _(I1)  (Eqn. 32-1) $\begin{matrix}{{V1} = \frac{r_{l1}{I1}}{1 + {g_{m1}r_{l1}}}} & \text{(Eqn.~~32-2)}\end{matrix}$

 V2=(I2−g _(m2) V1)r _(I2)  (Eqn. 33) $\begin{matrix}\begin{matrix}{{V3} = \quad {g_{m3}{V2r}_{l3}}} \\{= \quad {\left( {{I2} - {g_{m2}{V1}}} \right)r_{l2}g_{m3}r_{l3}}} \\{= \quad {\left( {{I2} - \frac{g_{m2}r_{l1}{I1}}{1 + {g_{m1}r_{l1}}}} \right)r_{l2}g_{m3}r_{l3}}}\end{matrix} & \text{(Eqn.~~33)}\end{matrix}$

when g_(m1)=g_(m2) and g_(m1)r_(I1)>>1, then we have $\begin{matrix}\begin{matrix}{{V3} = \quad {r_{l2}g_{m3}{r_{l3}\left( {{I2} - {I1}} \right)}}} \\{= \quad {R\left( {{I2} - {I1}} \right)}}\end{matrix} & \text{(Eqn.~~34)}\end{matrix}$

where the equivalent resistance R=r_(I2)g_(m3)r_(I3).

From the capacitance-to-frequency (C-F) converter 110/112, the currentdifference. I_(x)−I_(o), has been obtained and can be used as one of theinputs of I-V circuit 114. I2 can be generated using a similar principleused in the C-F converter. Using a reference capacitor, Cƒ, and outputvoltage V3 of the I-V circuit 114 to construct current mirrors as shownin FIG. 19 (compare FIG. 4), the current I2 can be obtained as$\begin{matrix}{I_{f} = {{{f\left( {{V3} - V_{T}} \right)}\left( {C_{f} + C_{stray} - C_{stray}} \right)} = {{f\left( {{V3} - V_{T}} \right)}C_{f}}}} & \text{(Eqn.~~35)}\end{matrix}$

The reference capacitor Cƒ is also called a feedback capacitor since thecurrent generated by Cƒ is related to the output voltage V3. In order toeliminate the effect of the stray capacitor connected to the Cƒ, onenull capacitor is connected to one of the current mirrors which has thesame routing as Cƒ. The V3 can be rewritten as: $\begin{matrix}\begin{matrix}{{V3} = \quad {R\left( {{I2} - {I1}} \right)}} \\{= \quad {R\left( {I_{x} - I_{o} - I_{f}} \right)}} \\{= \quad {R\left( {{K1C}_{x} - {K2C}_{o} - {K3C}_{f}} \right)}} \\{= \quad {R\left\lbrack {{{f\left( {V_{g} - V_{T}} \right)}C_{x}} - {{f\left( {V_{o} - V_{T}} \right)}C_{o}} -} \right.}} \\{\quad \left. {{f\left( {{V3} - V_{T}} \right)}C_{f}} \right\rbrack}\end{matrix} & \text{(Eqn.~~36-1)} \\{{V3} = \frac{{Rf}\left\lbrack {{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{o}} - {V_{T}C_{f}}} \right\rbrack}{1 + {RfC}_{f}}} & \text{(Eqn.~~36-2)}\end{matrix}$

if RƒC_(ƒ)>>1 then $\begin{matrix}{V_{out} = {{V3} = \frac{{\left( {V_{g} - V_{T}} \right)C_{x}} - {\left( {V_{o} - V_{T}} \right)C_{o}} - {V_{T}C_{f}}}{C_{f}}}} & \text{(Eqn.~~36-3)}\end{matrix}$

The output of the C-V converter 110/114 is independent of the clockfrequency and the value of the equivalent resistor. The sensitivity ofthe converter is defined as:

S _(Cx) =∂V/∂C _(x)=(V _(g) −V _(T))/C _(ƒ).  (Eqn. 37)

Thus, the sensitivity of the converter can be adjusted either by voltageV_(g) or capacitor C_(ƒ).

FIG. 20 is a graph illustrating the frequency and voltage outputs of thedual output converter 100. Each of the C-F and C-V converters 110/112and 110/114, respectively, are adjusted to have the best linearcharacteristics in the test range. The C/V converter is first adjustedby varying V_(o) to get the offset voltage greater than 1.5 v. The spanof the voltage output can be adjusted by changing the sensitivity of thecircuit, normally by shunting the feedback capacitor, C_(ƒ). Thefrequency output can be adjusted by varying capacitor C_(st), asdiscussed hereinabove. As illustrated in FIG. 20, the sensitivity of theC/V converter is 0.63 v/pF with non-linearity ±0.38% and the sensitivityof the C/F converter is 729 Hz/pF with non-linearity of ±0.61%. Thesensitivity of the C/V converter is lower than the designed valuebecause of large stray capacitance of C_(ƒ).

A dual output capacitance interface circuit (100) based on switchedcapacitor circuits and charge subtraction technique provides bothvoltage output (104) and frequency output (106). The circuit isprogrammable independently with sensitivity and offset adjustment, andis insensitive to fixed stray capacitance. A sensitivity of 350 Hz/pFhas been achieved in the 10 pF measurement range with non-linearity lessthat ±0.6%. A higher capacitance-to-frequency (C-F) sensitivity can beobtained for a smaller capacitance measurement range. A voltagesensitivity of 3-4 v/pF can be achieved. In the temperature range of 25°C.-95° C., the offset temperature drift of the C-V converter is lessthan 5%. The sensitivity drift is less than 3.5%. The offset temperaturedrift of the C-F converter is about −16% and the sensitivity drift isalso −16% in the temperature range of 25° C.-95° C.

A temperature compensation method is based on the fact that a MOSFET hasa bias voltage V_(GS) which can give the saturation current with azero-temperature-coefficient (ZTC). Using this principle, a temperaturecompensated clock generator is utilized. The temperature characteristicsof the clock frequency, which is related to the output frequency of theC-F converter, can be used to compensate the overall temperature errorof the converter. In the temperature range from 25° C. to 95° C., thetemperature coefficient of sensitivity, after temperature compensation,is 37 ppm/° C., and the temperature coefficient of offset is 86 ppm/° C.The extra current source results in a clock frequency with a positivetemperature coefficient. Since the C-F converter has negativetemperature coefficient and the output frequency is proportional to theclock frequency, the temperature error can be compensated. Measuredresults shows that after the compensation, the temperature drift, whenthe input capacitor is fixed as 6.6 pF, is ±0.3% and the sensitivitydrift is ±0.8%. An alternative temperature compensation method is to usean external MOS current source and a thermistor with a positivetemperature coefficient.

Although the invention has been illustrated and described in detail inthe drawings and foregoing description, the same is to be considered asillustrative and not restrictive in character, it being understood thatonly preferred embodiments have been shown and described, and that allchanges and modifications that come within the spirit of the inventionare desired to be protected. Undoubtedly, many other “variations” on the“themes” set forth hereinabove will occur to one having ordinary skillin the art to which the present invention most nearly pertains, and suchvariations are intended to be within the scope of the invention, asdisclosed herein.

What is claimed is:
 1. Dual output capacitance interface circuit forproviding at least one signal indicative of a capacitance value of acondition-sensitive capacitance; the dual output capacitance interfacecircuit comprising: a capacitance-to-current converter for providing acurrent signal indicative of the capacitance value of thecondition-sensitive capacitance; a current-to-voltage converter that isused to convert the current signal from the capacitance-to-currentconverter to a DC voltage output signal; and a current-to-frequencyconverter that is used to convert the current signal from thecapacitance-to-current converter to a frequency output signal, whereinthe current-to-frequency converter comprises a Schmitt trigger having aninput connected to the output of an oscillator comprised of currentmirrors that are switched by an output of the Schmitt trigger, toalternately charge and discharge a fixed capacitor using a mirroredcurrent that is proportional to the current signal from thecapacitance-to-current converter, thereby producing a Schmitt triggeroutput that provides a symmetric square wave output signal with afrequency determined by the condition-sensitive capacitance.
 2. Dualoutput capacitance interface circuit for providing at least two outputsignals indicative of a capacitance value of a condition-sensitivecapacitance; the dual output capacitance interface circuit comprising: acapacitance-to-current converter for providing a current signalindicative of the capacitance value of the condition-sensitivecapacitance; a current-to-voltage converter that is used to convert thecurrent signal from the capacitance-to-current converter to a DC voltageoutput signal; and a current-to-frequency converter that is used toconvert the current signal from the capacitance-to-current converter toa frequency output signal.